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參數(shù)資料
| 型號(hào)： | MC74HC76D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK Flip-Flop With Set and Reset |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大小： | 148K |
| 代理商： | MC74HC76D |
MC74HC76
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
AC CHARACTERISTICS
(CL = 50pF, Input tr = tf = 6ns)
V
Guaranteed Limit
Symbol
Parameter
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH,
tPHL
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
ns
tPLH,
tPHL
Maximum Propagation Delay, Set to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V, VEE = 0 V
35
pF
TIMING REQUIREMENTS
(Input tr = tf = 6ns)
V
Guaranteed Limit
Symbol
Parameter
VCC
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
tsu
Minimum Setup Time, J or K to Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to J or K
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE:For information on typical parametric values, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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