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參數(shù)資料
| 型號(hào)： | MC80C32-36SHXXX |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 22/83頁 |
| 文件大?。?/td> | 8336K |
| 代理商： | MC80C32-36SHXXX |
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20
8021G–AVR–03/11
ATmega329P/3290P
Figure 7-3.
On-chip Data SRAM Access Cycles
7.4
EEPROM Data Memory
The ATmega329P/3290P contains 1Kbytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see
7.4.1
EEPROM Write During Power-down Sleep Mode
When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the clock continues running, and as a
consequence, the device does not enter Power-down entirely. It is therefore recommended to
verify that the EEPROM write operation is completed before entering Power-down.
7.4.2
Preventing EEPROM Corruption
During periods of low V
CC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-
ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can
be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal
BOD does not match the needed detection level, an external low V
CC reset Protection circuit can
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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