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參數(shù)資料
| 型號： | MC80C52EXXX-12SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁數(shù)： | 90/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MC80C52EXXX-12SB |
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67
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor
control applications.
Figure 11-7. Phase Correct PWM Mode, Timing Diagram
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches
TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct PWM mode is shown on Figure 11-7. The TCNT0 value is in the timing diagram shown as a
histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used
to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02
bit is set. This option is not available for the OC0B pin (See Table 11-4 on page 70). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing
(or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and
setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements.
The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in the
phase correct PWM mode. If the OCR0x is set equal to BOTTOM, the output will be continuously low and if set equal to
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1
2
3
TCNTn
Period
OCnx
OCxn
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Update
f
OCnxPCPWM
f
clk_I/O
2
N
TOP
--------------------------------
=
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