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參數(shù)資料
| 型號： | MC80C52EXXX-12SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁數(shù)： | 91/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MC80C52EXXX-12SB |
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68
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
At the very start of period 2 in Figure 11-7 on page 67 OCnx has a transition from high to low even though there is no
Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
OCR0x changes its value from TOP, like in Figure 11-7 on page 67. When the OCR0x value is TOP the OCnx pin
value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the
OCnx value at TOP must correspond to the result of an up-counting Compare Match.
The timer starts counting from a value higher than the one in OCR0x, and for that reason misses the Compare
Match and hence the OCnx change that would have happened on the way up.
11.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the
following figures. The figures include information on when Interrupt Flags are set. Figure 11-8 on page 68 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other
than phase correct PWM mode.
Figure 11-8. Timer/Counter Timing Diagram, no Prescaling
Figure 11-9 on page 68 shows the same timing data, but with the prescaler enabled.
Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O/8)
Figure 11-10 on page 69 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
clk
Tn
(clk
I/O/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
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