參數(shù)資料
型號(hào): MC850DECZQ50BUR2
廠商: Freescale Semiconductor
文件頁數(shù): 25/72頁
文件大?。?/td> 0K
描述: IC MPU PQUICC 50MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 帶卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Bus Signal Timing
Table 7 provides interrupt timing for the MPC850.
Figure 22 provides the interrupt detection timing for the external level-sensitive lines.
Figure 22. Interrupt Detection Timing for External Level Sensitive Lines
Figure 23 provides the interrupt detection timing for the external edge-sensitive lines.
Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines
Table 7. Interrupt Timing
Num
Characteristic 1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
direct relation with the total system interrupt latency that the MPC850 is able to support
50 MHz
66MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
I39
IRQx valid to CLKOUT rising edge (set up time)
6.00
6.00
6.00
ns
I40
IRQx hold time after CLKOUT.
2.00
2.00
2.00
ns
I41
IRQx pulse width low
3.00
3.00
3.00
ns
I42
IRQx pulse width high
3.00
3.00
3.00
ns
I43
IRQx edge-to-edge time
80.00
121.0
100.0
ns
CLKOUT
IRQx
I39
I40
CLKOUT
IRQx
I39
I41
I42
I43
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