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| 型號： | MC8641DHX1000GE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 29/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL CORE PROCESSOR 1023-CBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.0GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
124
Freescale Semiconductor
System Design Information
The COP interface has a standard header, shown in Figure 67, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header shown in Figure 67; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 67 is common to all known emulators.
For a multi-processor non-daisy chain configuration, Figure 68, can be duplicated for each processor. The
recommended daisy chain configuration is shown in Figure 69. Please consult with your tool vendor to
determine which configuration is supported by their emulator.
20.9.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
TRST should be tied to HRESET through a 0 k
Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 68. If this is not possible, the isolation resistor will allow future access to TRST
in case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OVDD through a 10 kΩ resistor. This will prevent TCK from changing state and
reading incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
Figure 67. COP Connector Physical Pinout
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
1
2
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
GND
COP_TCK
COP_TMS
COP_SRESET
COP_HRESET
COP_CHKSTP_OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC8572VTAVND | MPU POWERQUICC III 1023-PBGA |
| MPC8572VTAVNB | MPU POWERQUICC III 1023-PBGA |
| MPC8572VTAULB | MPU POWERQUICC III 1023-PBGA |
| MPC8572VTATLB | MPU POWERQUICC III 1023-PBGA |
| MPC8572VTARLD | MPU POWERQUICC III 1023-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8641DHX1000H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DHX1000J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DHX1000K | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DHX1000N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DHX1000NB | 功能描述:微處理器 - MPU G8 REV 2.0 0.95V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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