參數資料
型號： MC8641DHX1000GE
廠商： Freescale Semiconductor
文件頁數： 47/130頁
文件大小： 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，FCCBGA
供應商設備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
23
DDR and DDR2 SDRAM
6.2
DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR SDRAM Input AC Timing Specifications
Table 18 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V.
Table 19 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V.
Table 20 provides the input AC timing specifications for the DDR SDRAM interface.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
400, 533 MHz
600 MHz
VIL
—D
n_MVREF – 0.25
D
n_MVREF – 0.20
V—
AC input high voltage
400, 533 MHz
600 MHz
VIH
D
n_MVREF + 0.25
D
n_MVREF + 0.20
—
V—
Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—D
n_MVREF – 0.31
V
—
AC input high voltage
VIH
D
n_MVREF + 0.31
—
V
—
Table 20. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for
MDQS—MDQ/MECC
tCISKEW
—ps
1, 2
600 MHz
—
–240
240
—
3
533 MHz
—
–300
300
—
3
400 MHz
—
–365
365
—
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding
bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and
abs(tCISKEW) is the absolute value of tCISKEW.
3. Maximum DDR1 frequency is 400 MHz.
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