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參數(shù)資料
| 型號： | MC88LV915TFN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MC88LV915TFN |
MC88LV915T
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
35
FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V)
Symbol
Parameter
Guaranteed Minimum
Unit
Fmax (2X_Q)
Maximum Operating Frequency, 2X_Q Output
100
MHz
Fmax (‘Q’)
Maximum Operating Frequency,
Q0–Q3 Outputs
50
MHz
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50 Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)
0.5
2.0
ns
Into a 50
Load
Terminated to VCC/2
tPULSE WIDTH
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5 1
0.5tCYCLE + 0.5 1
ns
Into a 50
Load
Terminated to VCC/2
tPULSE WIDTH
(2X_Q Output)
Output Pulse Width:
40MHz
2X_Q @ 1.5V
66MHz
80MHz
100MHz
0.5tCYCLE – 1.5
0.5tCYCLE – 1.0
0.5tCYCLE + 0.5
ns
Into a 50
Load
Terminated to VCC/2
tCYCLE
(2x_Q Output)
Cycle–to–Cycle Variation
40MHz
2x_Q @ VCC/2
66MHz
80MHz
100MHz
tCYCLE – 600ps
tCYCLE – 300ps
tCYCLE – 400ps
tCYCLE + 600ps
tCYCLE + 300ps
tCYCLE + 400ps
tPD2
SYNC F
db
k
(With 1M
from RC1 to An VCC)
ns
SYNC Feedback
SYNC Input to Feedback Delay 66MHz
(Measured at SYNC0 or 1 and
80MHz
FEEDBACK Input Pins)
100MHz
–1.65
–1.45
–1.25
–1.05
–0.85
–0.65
tSKEWr3
(Rising) See Note 4
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWf3
(Falling)
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
750
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWall3
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
—
750
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tLOCK4
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL5
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
tPHZ,tPLZ5
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1F, tLOCK minimum is
with C1 = 0.01
F.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
2
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