參數(shù)資料
型號： MC92600JUB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝： 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁數(shù)： 33/98頁
文件大?。?/td> 1288K
代理商： MC92600JUB
MOTOROLA
Chapter 3. Receiver
3-11
Device Operations
This allows in-system loop-back BIST independent of the current input state. See Chapter 5
for more information on test modes.
The input amplier’s electrical specications may be found in Table 6-3, "DC Electrical
3.5.2
8B/10B Decoder Operation
The 8B/10B decoder takes the 10-bit character from the transition tracking loop and
decodes it according to the 8B/10B coding standard [1,2]. The decoder does two types of
error checking. First it checks that all characters are a legal member of the 8B/10B coding
space. The decoder also checks for running disparity errors. If the running disparity exceeds
the limits set in the 8B/10B coding standard then a disparity error is generated. See
An illegal character or disparity error sets the RECV_x_ERR signal high, coincident with
the received data for a 1-byte output period. The “Code Error” or “Disparity Error” is
reported as described in Section 3.6, “Receiver Interface Error Codes.” It is difcult to
determine the exact byte that caused the disparity error, so it should not be associated with
a particular received byte. It is rather a general indicator of the improper operation of the
link. Its intended use is for the system to monitor link reliability.
The 8B/10B decoder is bypassed when operating in 10-bit interface mode (TBIE = high.)
3.5.3
Transition Tracking Loop and Data Recovery
The received differential data from the input amplier is sent to the transition tracking loop
for data recovery. The MC92600 uses an oversampled transition tracking loop method for
data recovery. The differentially received data is sampled and processed digitally providing
for low bit error rate (better than 10 -12) data recovery of a distorted bit stream.
The transition tracking loop is tolerant of frequency offset between the transmitter and
receiver. The MC92600 reliably operates with +250 ppm of frequency offset. The
MC92600 is tolerant of frequency offset between the transmitter and receiver. The
MC92600 reliably operates with +250 ppm of frequency offset. The device’s transition
tracking loop method is different than the typical PLL clock recovery method. Its receiver
compensates for overrun and underrun caused by frequency offset by modulating the
duty-cycle and period of the received byte clock.
Recovered data is accumulated into 10-bit characters. Characters are aligned to their
original 10-bit boundaries if a byte alignment mode is enabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC92600ZTB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
MC92600CJUB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
MC92600ZTB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
MC92600JUB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
MC92602ZTA SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
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