參數(shù)資料
型號(hào): MC92600JUB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝: 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁(yè)數(shù): 60/98頁(yè)
文件大?。?/td> 1288K
代理商: MC92600JUB
MOTOROLA
Chapter 6. Electrical Specications and Characteristics
6-9
AC Electrical Characteristics
6.3.3
Receiver Recovered Clock Timing
The timing diagram for the recovered clock is shown in Figure 6-8.
Figure 6-8. Recovered Clock Timing Diagram
Table 6-12 shows the timing specications for the recovered clock.
TL
REF_CLK pulse width low2
3.2
ns
frange
REF_CLK frequency range 3
REF_CLK frequency range 4
REF_CLK frequency range 5
95
135
MHz
47.5
67.5
MHz
23.75
33.75
MHz
TD
REF_CLK duty cycle 6
REF_CLK duty cycle 7
40
60
%
45
55
%
foffset
REF_CLK to REF_CLK frequency offset
-250
250
ppm
Tj
REF_CLK input jitter 8
-80
ps
Tlock
PLL lock time 9
-
20,480 +
25
s
bit-times
1 Measured between 10-90% points.
2 Measured between 50-50% points.
3 Full speed (HSE = Low), normal data rate (DDRE = Low).
4 Half speed (HSE = High), normal data rate (DDRE = Low); and full speed (HSE = Low), double data rate (DDRE =
High).
5 Half speed (HSE = High), double data rate (DDRE = High).
6 Normal data rate (DDRE = Low).
7 Double data rate (DDRE = High).
8 Total peak-to-peak jitter
9 Lock time after compliant REF_CLK signal applied.
Table 6-11. Reference Clock Specication (continued)
Symbol
Characteristic
Min
Max
Unit
RECV_x_RCLK
Tlrck
Trck
Tsrck
Tf, Tr
F
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e
sc
a
le
S
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m
ic
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n
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c
to
r,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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