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| 型號： | MC92600ZTB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, PLASTIC, MAPBGA-196 |
| 文件頁數(shù)： | 25/98頁 |
| 文件大小： | 1288K |
| 代理商： | MC92600ZTB |
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MOTOROLA
Chapter 3. Receiver
3-3
Receiver Interface Signals
Table 3-1. MC92600 Receiver Interface Signals
Signal Name
Description
Function
Direction
Active
State
RECV_x_7 through
RECV_x_0
Received byte (bits 7–0) Received and decoded data/control
byte.
The least signicant 8 bits of received
coded data in TBI mode.
Output
—
RECV_x_K
Special data indicator/
Received bit 8
Indicates that received byte is a special
control byte.
Received coded bit 8 in TBI mode.
Errors are coded using this signal. See
Section 3.6 for error codes.
Output
—
RECV_x_9
Received bit 9
Received coded bit 9 in TBI mode.
Unused in 8-bit mode.
Output
—
RECV_x_IDLE
Receiver idle detect
Indicates that the receiver detected an
idle character (operates in Byte and TBI
modes).
Errors are coded using this signal. See
Section 3.6 for error codes.
Output
—
RECV_x_ERR
Receiver error
Indicates that the receiver detected an
error. RECV_x_IDLE and RECV_x_K
must be decoded to determine error
condition. See Section 3.6 for error
codes.
Output
—
RECV_x_RCLK
Receiver recovered
Byte clock
Internally generated clock used for
reading receiver outputs when RCCE is
asserted.
Output
—
WSE_GEN
Word synchronization
Event generate
This signal when asserted coincident
with XMIT_x_K set low on all four links
invalidates current byte alignment and
word synchronization.
This signal also affects transmitter
operation. See Section 2.2.
Input
—
XMIT_x_K
Special data indicator
This signal when set low on all four links
coincident with WSE_GEN asserted
invalidates current byte alignment and
word synchronization.
This signal also affects transmitter
operation. See Section 2.2.
Input
—
TBIE
10-bit interface enable
Indicates that the receiver interface is in
10-bit mode and that the 8B/10B
decoder is bypassed.
Input
High
HSE
half-speed enable
Indicates to operate link at half-speed.
Both data and link interfaces run at half
speed.
Input
High
WSE
Word synchronization
enable
Indicates that all four receivers are
being used in unison to receive
synchronized data.
Input
High
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