參數(shù)資料
型號: MC92600ZTB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝: 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, PLASTIC, MAPBGA-196
文件頁數(shù): 42/98頁
文件大?。?/td> 1288K
代理商: MC92600ZTB
MOTOROLA
Chapter 4. System Design Considerations
4-5
Conguration and Control Signals
source and re-establishing synchronization. All word synchronization modes are supported
in repeater mode.
Similar to byte alignment, the word synchronization sequence must be repeated twice, once
for the repeater and once for the destination’s receiver. If the 4 idle/1 non-idle word
synchronization event mode is being used, a 4 idle/1 non-idle word synchronization event
must be followed by a second 4 idle/1 non-idle word synchronization event to enable the
entire link to establish word synchronization. Note that byte alignment must be established
4.4.4
Recovered Clock Mode
The MC92600 Quad’s four transmitters are timed exclusively to the reference clock
domain. Recovered clock mode cannot be used in repeater mode. The setting on the
recovered clock enable input, RCCE, is ignored when in repeater mode and all data is timed
to the reference clock.
4.4.5
Add/Drop Idle Mode
Repeater mode is timed exclusively to the reference clock domain as stated above. A
frequency offset between the source transmitter and the repeater will cause the repeater’s
receiver to eventually overrun/underrun. To ensure that overrun/underrun does not cause
data to be lost, add/drop idle mode must be used. Add/drop idle mode is enabled by setting
ADIE high. The repeater adds or drops idles from the data stream to maintain alignment to
the reference clock. The guidelines for idle density are discussed in Section 3.4.2,
4.4.6
Half-Speed Mode, Double Data Rate Mode
Half-speed mode and double data rate mode simply affect the frequency of the reference
clock that must be provided and the timing of the receiver interface. All combinations of
these modes are supported in repeater mode. See Section 3.5.4.4, “Half-Speed Mode” for
more information on half-speed mode and Section 3.5.4.3, “Double Data Rate Mode” for
more information on double data rate mode.
4.5
Conguration and Control Signals
The MC92600 has many conguration and control signals that are asynchronous to all
inputs clocks. Most of the signals affect internal conguration state and must be set at
power-up. If their state is changed after power-up, some require that the chip be reset by
setting RESET low and then releasing high. While other conguration signals are meant to
be changed during normal operation and do not require chip reset. However, these signals
may still affect device operation. Table 4-4 lists all of the MC92600 asynchronous
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC92600CJUB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
MC92600ZTB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
MC92600JUB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
MC92602ZTA SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
MC9S08AC16CFDE 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, BCC48
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