參數(shù)資料
型號(hào): MC9328MX1CVM15
廠商: Freescale Semiconductor
文件頁數(shù): 93/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX 150MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 152
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 256-MAPBGA
包裝: 托盤
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
92
Freescale Semiconductor
4.17
CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32
× 32 image data receive
FIFO, and a 16
× 32 statistic data FIFO.
4.17.1
Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 69 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 42.
Figure 68. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
2 There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 – PC24). When SSI signals
are configured as outputs, they can be viewed at Port C alternate function a. When SSI signals are configured as inputs, the
SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input is selected
from Port C alternate function.
3
bl = bit length; wl = word length
VSYNC
HSYNC
PIXCLK
DATA[7:0]
Valid Data
2
1
7
5
6
3
4
Valid Data
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