參數(shù)資料
型號： MC9328MX21DVK
廠商： Freescale Semiconductor
文件頁數(shù)： 19/100頁
文件大?。?/td> 0K
描述： IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝： 152
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -30°C ~ 70°C
封裝/外殼： 289-LFBGA
包裝： 托盤
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
25
Figure 9. BMI Drives Clock, MMD Write BMI Timing
(MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1)
Note:
The BMI_CLK/CS can only be up to 30MHz if BMI latch data at the falling edge and can be up to 36MHz (double as max
data pad speed) if BMI latch data at the next rising edge.
Note:
Tds1 is the receive data setup time when BMI latch data at the falling edge.
Note:
Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2
Connecting BMI to External Bus Master Devices
In this mode both MASTER_SEL bit and MMD_MODE_SEL bit are cleared and the MMD_CLKOUT
bit is no useful. BMI_WRITE and BMI_CLK/CS are input signals driving by the external bus master. The
Output signal BMI_READ_REQ can be used as an interrupt signal to inform external bus master that data
is ready in the BMI TxFIFO for a read access. The external bus master can write data to the BMI RxFIFO
anytime since the CPU or DMA can move data out from RxFIFO much faster than the BMI interface. An
overflow interrupt is generated if RxFIFO overflow is detected. Once this happens, the new coming data
is ignored.
Each falling edge of BMI_CLK/CS will determine if the current cycle is read or write cycle. It drives data
and enables data out if BMI_WRITE is logic high. The D_EN signal remains active only while BMI_CLK/
CS is logic low and BMI_WRITE is logic high.
Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus.
Table 17. MMD Write BMI Timing Table when BMI Drives Clock
Item
Symbol
Minimum
Typical
Maximum
Unit
Receive data setup time1
Tds1
14
–
ns
Receive data setup time2
Tds2
14
–
ns
Can be asserted any time
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
RxD1
RxD2
Last RxD
Tds1
Tds2
A 1 is written to READ bit of control register
Total has COUNT+1 clocks in one burst
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MX21DVK 制造商:Freescale Semiconductor 功能描述:Microprocessor
MC9328MX21DVKR2 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21DVM 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21DVMR2 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21S 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX family of microprocessors 266 MHz
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