參數(shù)資料
型號(hào): MC9328MX21SCVM
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289
封裝: 17 X17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-289
文件頁(yè)數(shù): 10/88頁(yè)
文件大?。?/td> 975K
代理商: MC9328MX21SCVM
MC9328MX21S Technical Data, Rev. 1.3
18
Freescale Semiconductor
Specifications
3.7
External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to
request the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External
request is the source (as per the RSSR settings) becomes the current highest priority channel. The external
device using the External DMA request should keep its request asserted until it is serviced by the DMAC.
One External DMA request will initiate one DMA burst.
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
The DMA channel for which the DMA burst is ongoing has request source as external DMA Request
(as per source select register setting).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External
DMA request is de-asserted immediately after sensing grant signal active.
Table 12. Reset Module Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.10 V 3.0 V ± 0.30 V
Unit
Min
Max
Min
Max
1
Width of input POWER_ON_RESET
800
800
ms
2
Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
300
ms
3
7k to 32k-cycle stretcher for SDRAM reset
7
Cycles of CLK32
4
14k to 32k-cycle stretcher for internal system reset HRESERT
and output reset at pin RESET_OUT
14
Cycles of CLK32
5
Width of external hard-reset RESET_IN
4
4
Cycles of CLK32
6
4k to 32k-cycle qualifier
4
Cycles of CLK32
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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