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參數資料
| 型號： | MC9328MX21SCVM |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289 |
| 封裝： | 17 X17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MAPBGA-289 |
| 文件頁數： | 56/88頁 |
| 文件大?。?/td> | 975K |
| 代理商： | MC9328MX21SCVM |
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MC9328MX21S Technical Data, Rev. 1.3
6
Freescale Semiconductor
Signal Descriptions
CAS
SDRAM Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
Clocks and Resets
EXTAL26M
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
XTAL26M
Oscillator output to external crystal. When using an external signal source, float this output.
EXTAL32K
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
XTAL32K
Oscillator output to external crystal. When using an external signal source, float this output.
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
EXT_48M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
TEST_WB[2:0]
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
TEST_WB[4:3]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
WKGD
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “
JTAG pinouts” in the Multi-ICE User Guide from ARM Limited.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
Table 2. i.MX21S Signal Descriptions (Continued)
Signal Name
Function/Notes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC9328MX21SCVMR2 | 功能描述:處理器 - 專門應用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVK | 功能描述:處理器 - 專門應用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVKR2 | 功能描述:處理器 - 專門應用 DB I.MX21S RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVM | 功能描述:處理器 - 專門應用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21SVMR2 | 功能描述:處理器 - 專門應用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數據緩存: 數據 RAM 大小:128 KB 數據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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