- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10953 > MC9328MX21SVM (Freescale Semiconductor)IC MPU I.MX21S 289-MAPBGA PDF資料下載
參數(shù)資料
| 型號： | MC9328MX21SVM |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 45/88頁 |
| 文件大小： | 0K |
| 描述： | IC MPU I.MX21S 289-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | i.MX21 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 266MHz |
| 連通性： | 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 289-LFBGA |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
Signal Descriptions
MC9328MX21S Technical Data, Rev. 1.3
Freescale Semiconductor
5
Table 2. i.MX21S Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [25:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
OE
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 K
Ω resister to ground. For a logic
high, terminate with a 1 K
Ω resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals
A[20:16].
SDIBA [3:0]
SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address
signals A[24:21].
MA [11:0]
SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].
DQM [3:0]
SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2
corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].
CSD0
SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
CSD1
SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
RAS
SDRAM Row Address Select signal.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX21
Product
Family
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCF5373LCVM240J | IC MPU RISC 240MHZ 196MABGA |
| MCF52274CLU120 | MCU 32-BIT LCD TOUCH 176-LQFP |
| HR25A-9J-20P | CONN JACK 20POS MALE SOLDER |
| MCF5373LCVM240 | IC MCU 32BIT 240MHZ 196-MAPBGA |
| JBXFD0G02MSSDSMR | CONN PLUG 2POS STRAIGHT SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21SVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21VG | 制造商:Rochester Electronics LLC 功能描述:APPLICATIONS PROCESSOR - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21VH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21VK | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21VK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。