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參數(shù)資料
型號(hào): MC9S08MP12VWL
廠商: Freescale Semiconductor
文件頁數(shù): 15/36頁
文件大小: 0K
描述: MCU 8BIT .25U SGF FLASH SOIC
標(biāo)準(zhǔn)包裝: 26
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 51.34MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 12KB(12K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b,D/A 3x5b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
MC9S08MP16 Series Data Sheet, Rev. 2
Electrical Characteristics
Freescale Semiconductor
22
4
P
DCO output frequency range —
trimmed 2
Low range (DRS=00)
fdco_t
16
20
MHz
C
Mid range (DRS=01)
32
40
P
High range (DRS=10)
48
60
5
P
DCO output frequency 2
Reference = 32768 Hz and
DMX32 = 1
Low range (DRS=00)
fdco_DMX32
19.92
MHz
P
Mid range (DRS=01)
39.85
P
High range (DRS=10)
59.77
6C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
fdco_res_t
0.1
0.2
%fdco
7C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
fdco_res_t
0.2
0.4
%fdco
8P
Total deviation of trimmed DCO output frequency over voltage and
temperature
fdco_t
0.8
2
%fdco
9C
Total deviation of trimmed DCO output frequency over fixed voltage
and temperature range of 0
C to 70 C
fdco_t
0.5
1
%fdco
10
C FLL acquisition time 3
tAcquire
——
1
ms
11
C Long term jitter of DCO output clock (averaged over 2-ms interval) 4
CJitter
0.02
0.2
%fdco
1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value.
2 The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given
interval.
Table 10. ICS Frequency Specifications (continued)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
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