where K is a constant pertaining to the pa" />
參數(shù)資料
型號: MC9S08MP12VWL
廠商: Freescale Semiconductor
文件頁數(shù): 3/36頁
文件大?。?/td> 0K
描述: MCU 8BIT .25U SGF FLASH SOIC
標(biāo)準(zhǔn)包裝: 26
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 51.34MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b,D/A 3x5b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Electrical Characteristics
MC9S08MP16 Series Data Sheet, Rev. 2
Freescale Semiconductor
11
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
2.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human
Body
Series resistance
R1
1500
Storage capacitance
C
100
pF
Number of pulses per pin
3
Latch-up
Minimum input voltage limit
– 2.5
V
Maximum input voltage limit
7.5
V
Table 6. ESD and Latch-Up Protection Characteristics
No.
Rating1
1 Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
2000
V
2
Charge device model (CDM)
VCDM
500
V
3
Latch-up current at TA = 125CILAT
100
mA
Table 7. DC Characteristics
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
1
— Operating Voltage
VDD
2.7
5.5
V
2
— Analog Supply voltage delta to VDD (VDD –VDDA)
(2)
V
DDA
—0
100
mV
3
— Analog Ground voltage delta to VSS (VSS –VSSA)
V
SSA
—0
100
mV
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