- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45290 > MC9S08RE32FJE (FREESCALE SEMICONDUCTOR INC) 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MC9S08RE32FJE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 190/234頁 |
| 文件大?。?/td> | 1758K |
| 代理商： | MC9S08RE32FJE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁當(dāng)前第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁
Resets, Interrupts, and System Conguration
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
59
as an edge on the IRQ pin or a timer-overow event. The debug module can also generate an SWI under
certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status ag will become set. The
CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I
bit in the CCR is logic 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set
after reset, which masks (prevents) all maskable interrupt sources. The user program initializes the stack
pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualied interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence uses the same cycle-by-cycle sequence as the SWI instruction and
consists of:
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the rst three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared
inside an ISR (after clearing the status ag that generated the interrupt) so that other interrupts can be
serviced without waiting for the rst service routine to nish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difcult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that restores the CCR, A,
X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.
NOTE
For compatibility with the M68HC08 Family, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it just before the RTI that is used to return from the ISR.
If two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced rst
(see Table 5-1).
5.5.1
Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack, which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9S08RD16CFGE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08RD32FDE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC48 |
| MC9S08RD8FJE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| MC9S08RD8FDE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC48 |
| MC9S08RC60FJE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9S08RE32PE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RE60 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RE60CDWE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RE60CFDE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RE60CFG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。