Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
98
Freescale Semiconductor
BCLR n,opr8a
Clear Bit n in Memory
Mn
← 0
–––––– DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
5
BCS rel
Branch if Carry Bit Set
(Same as BLO)
Branch if (C) = 1
–––––– REL
25 rr
3
BEQ rel
Branch if Equal
Branch if (Z) = 1
–––––– REL
27 rr
3
BGE rel
Branch if Greater Than or
Equal To
(Signed Operands)
Branch if (N
⊕ V) = 0
––––––
REL
90 rr
3
BGND
Enter Active Background
if ENBDM = 1
Waits For and Processes BDM
Commands Until GO, TRACE1, or
TAGGO
––––––
INH
82
5+
BGT rel
Branch if Greater Than
(Signed Operands)
Branch if (Z) | (N
⊕ V) = 0
–––––– REL
92 rr
3
BHCC rel
Branch if Half Carry Bit
Clear
Branch if (H) = 0
–––––– REL
28 rr
3
BHCS rel
Branch if Half Carry Bit
Set
Branch if (H) = 1
–––––– REL
29 rr
3
BHI rel
Branch if Higher
Branch if (C) | (Z) = 0
–––––– REL
22 rr
3
BHS rel
Branch if Higher or Same
(Same as BCC)
Branch if (C) = 0
–––––– REL
24 rr
3
BIH rel
Branch if IRQ Pin High
Branch if IRQ pin = 1
–––––– REL
2F rr
3
BIL rel
Branch if IRQ Pin Low
Branch if IRQ pin = 0
––––– – REL
2E rr
3
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test
(A) & (M)
(CCR Updated but Operands
Not Changed)
0––
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9ED5
9EE5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
3
5
4
BLE rel
Branch if Less Than
or Equal To
(Signed Operands)
Branch if (Z) | (N
⊕ V) = 1
–––––
–
REL
93 rr
3
BLO rel
Branch if Lower
(Same as BCS)
Branch if (C) = 1
–––––– REL
25 rr
3
BLS rel
Branch if Lower or Same
Branch if (C) | (Z) = 1
––––– – REL
23 rr
3
BLT rel
Branch if Less Than
(Signed Operands)
Branch if (N
⊕ V ) = 1
––––– – REL
91 rr
3
BMC rel
Branch if Interrupt Mask
Clear
Branch if (I) = 0
––––– – REL
2C rr
3
BMI rel
Branch if Minus
Branch if (N) = 1
––––– – REL
2B rr
3
BMS rel
Branch if Interrupt Mask
Set
Branch if (I) = 1
––––– – REL
2D rr
3
BNE rel
Branch if Not Equal
Branch if (Z) = 0
––––– – REL
26 rr
3
BPL rel
Branch if Plus
Branch if (N) = 0
––––– – REL
2A rr
3
BRA rel
Branch Always
No Test
––––– – REL
20 rr
3
Table 7-2. HCS08 Instruction Set Summary (Sheet 2 of 7)
Source
Form
Operation
Description
Effect
on CCR
Ad
dress
Mode
Opcode
Operand
Bus
Cyc
les
1
VH I N Z C