參數(shù)資料
型號: MC9S12B64MPV16
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP112
封裝: LQFP-112
文件頁數(shù): 83/132頁
文件大?。?/td> 1842K
代理商: MC9S12B64MPV16
Device User Guide — 9S12B128DGV1/D V01.13
54
2.2.2 RESET — External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up
state, and an output when an internal MCU function causes a reset.
2.2.3 TEST — Test Pin
This input only pin is reserved for test.
NOTE:
The TEST pin must be tied to VSS in all applications.
2.2.4 VREGEN — Voltage Regulator Enable Pin
This input only pin enables or disables the on-chip voltage regulator.
2.2.5 XFC — PLL Loop Filter Pin
PLL loop filter. Please ask your Motorola representative for the interactive application note to compute
PLL loop filter elements. Any current leakage on this pin must be avoided.
Figure 2-3 PLL Loop Filter Connections
2.2.6 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.
2.2.7 PAD[15:0] / AN[15:0] — Port AD Input Pins ATD
PAD15 - PAD0 are general purpose input pins and analog inputs AN[15:0] of the analog to digital
converter ATD.
MCU
XFC
R0
CS
CP
VDDPLL
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