
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
275
Rev 01.24
Figure 9-23. Wait Mode Entry/Exit Sequence
Enter
Wait Mode
PLLWAI=1
?
Exit Wait w.
CMRESET
Exit Wait w.
ext.RESET
Exit
Wait Mode
Enter
SCM
Exit
Wait Mode
Core req’s
Wait Mode.
CWAI or
SYSWAI=1
?
SYSWAI=1
?
Clear
PLLSEL,
Disable PLL
Disable
core clocks
Disable
system clocks
CME=1
?
INT
?
CM fail
?
SCME=1
?
SCMIE=1
?
Continue w.
normal OP
no
yes
no
yes
Wait Mode left
due to external
reset
Generate
SCM Interrupt
(Wakeup from Wait)
SCM=1
?
Enter
SCM
no
yes