
MC9S12DT128B Device User Guide — V01.09
A.7 SPI
A.7.1 Master Mode
Figure A-5 SPI Master Timing (CPHA = 0)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
1
9
5
6
MSB IN2
BIT 6 . . . 1
LSB IN
MSB OUT2
LSB OUT
BIT 6 . . . 1
10
4
2
9
(CPOL
= 0)
(CPOL
= 1)
3
11
12
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.