參數(shù)資料
    型號: MC9S12DB128BVPV
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
    封裝: LQFP-112
    文件頁數(shù): 41/128頁
    文件大小: 2183K
    代理商: MC9S12DB128BVPV
    MC9S12DT128B Device User Guide — V01.09
    Revision History
    Version
    Number
    Revision
    Date
    Effective
    Date
    Author
    Description of Changes
    V01.00
    18 Jun
    2001
    18 June
    2001
    Initial version (parent doc v2.03 dug for dp256).
    V01.01
    23 July
    2001
    23 July
    2001
    Updated version after review
    V01.02
    23 Sep
    2001
    23 Sep
    2001
    Changed Partname, added pierce mode, updated electrical
    characteristics
    some minor corrections
    V01.03
    12 Oct
    2001
    12 Oct
    2001
    Replaced Star12 by HCS12
    V01.04
    27 Feb
    2002
    27 Feb
    2002
    Updated electrical spec after MC-Qualication (IOL/IOH), Data for
    Pierce, NVM reliability
    New document numbering. Corrected Typos
    V01.05
    4 Mar
    2002
    4 Mar
    2002
    Increased VDD to 2.35V, removed min. oscillator startup
    Removed Document order number except from Cover Sheet
    V01.06
    8 July
    2002
    22 July
    2002
    Added:
    Pull-up columns to signal table,
    example for PLL Filter calculation,
    Thermal values for junction to board and package,
    BGND pin pull-up
    Part Order Information
    Global Register Table
    Chip Conguration Summary
    Modied:
    Reduced Wait and Run IDD values
    Mode of Operation chapter
    changed leakage current for ADC inputs down to +-1uA
    Corrected:
    Interrupt vector table enable register inconsistencies
    PCB layout for 80QFP VREGEN position
    V01.07
    16 Aug
    2002
    16 Aug
    2002
    Minor corrections in table 1-1 & section 1.5.1
    V01.08
    12 Sep
    2002
    12 Sep
    2002
    Corrected register address mismatches in section 1.5.1
    V01.09
    31 Oct
    2002
    31 Oct
    2002
    Removed document order no. from Revision History page
    Renamed "Preface" section to "Derivative Differences and
    Document references". Added details for derivatives missing CAN1,
    BDLC, IIC and/or Byteight
    Added oscillator clock connection to BDM in S12_CORE in g 3-1
    Section HCS12 Core Block Description: mentioned alternate clock
    of BDM to be equivalent to oscillator clock
    Corrected several register and bit names in “Local Enable” column
    of Table 5.1 Interrupt Vector Locations.
    Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
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    Freescale Semiconductor, Inc.
    For More Information On This Product,
    Go to: www.freescale.com
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