Chapter 13 Timer Module (TIM16B4CV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
419
13.3
Memory Map and Register Denition
This section provides a detailed description of all memory and registers.
13.3.1
Module Memory Map
The memory map for the TIM16B4CV1 module is given below in
Table 13-1. The address listed for each
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B4CV1 module and the address offset for each register.
Table 13-1. TIM16B4CV1 Memory Map
Address Offset
Use
Access
0x0000
Timer Input Capture/Output Compare Select (TIOS)
R/W
0x0001
Timer Compare Force Register (CFORC)
R/W1
1
Always read 0x0000.
0x0002
Output Compare 7 Mask Register (OC7M)
R/W
0x0003
Output Compare 7 Data Register (OC7D)
R/W
0x0004
Timer Count Register (TCNT(hi))
R/W2
0x0005
Timer Count Register (TCNT(lo))
R/W2
0x0006
Timer System Control Register1 (TSCR1)
R/W
0x0007
Timer Toggle Overow Register (TTOV)
R/W
0x0008
Timer Control Register1 (TCTL1)
R/W
0x0009
Reserved
— 3
0x000A
Timer Control Register3 (TCTL3)
R/W
0x000B
Reserved
— 3
0x000C
Timer Interrupt Enable Register (TIE)
R/W
0x000D
Timer System Control Register2 (TSCR2)
R/W
0x000E
Main Timer Interrupt Flag1 (TFLG1)
R/W
0x000F
Main Timer Interrupt Flag2 (TFLG2)
R/W
0x0010 - 0x0017
Reserved
— 3
0x0018
Timer Input Capture/Output Compare Register4 (TC4(hi))
R/W4
0x0019
Timer Input Capture/Output Compare Register 4 (TC4(lo))
R/W4
0x001A
Timer Input Capture/Output Compare Register 5 (TC5(hi))
R/W4
0x001B
Timer Input Capture/Output Compare Register 5 (TC5(lo))
R/W4
0x001C
Timer Input Capture/Output Compare Register 6 (TC6(hi))
R/W4
0x001D
Timer Input Capture/Output Compare Register 6 (TC6(lo))
R/W4
0x001E
Timer Input Capture/Output Compare Register 7 (TC7(hi))
R/W4
0x001F
Timer Input Capture/Output Compare Register 7 (TC7(lo))
R/W4
0x0020
16-Bit Pulse Accumulator Control Register (PACTL)
R/W
0x0021
Pulse Accumulator Flag Register (PAFLG)
R/W
0x0022
Pulse Accumulator Count Register (PACNT(hi))
R/W
0x0023
Pulse Accumulator Count Register (PACNT(lo))
R/W
0x0024 – 0x002C Reserved
— 3
0x002D
Timer Test Register (TIMTST)
R/W2
0x002E – 0x002F Reserved
— 3