Chapter 26 384 Kbyte Flash Module (S12XFTM384K2V1)
MC9S12XE-Family Reference Manual , Rev. 1.13
Freescale Semiconductor
1027
26.3.2.10 P-Flash Protection Restrictions
The general guideline is that P-Flash protection can only be added and not removed.
Table 26-22 specifies
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
26.3.2.11 EEE Protection Register (EPROT)
The EPROT register denes which buffer RAM EEE partition areas are protected against writes.
All bits in the EPROT register are readable and writable except for RNV[6:4] which are only readable. The
EPOPEN and EPDIS bits can only be written to the protected state. The EPS bits can be written anytime
until the EPDIS bit is cleared. If the EPOPEN bit is cleared, the state of the EPDIS and EPS bits is
irrelevant.
During the reset sequence, the EPROT register is loaded from the EEE protection byte in the Flash
configuration field at global address 0x7F_FF0D located in P-Flash memory (see
Table 26-3) as indicated
by reset condition F in
Figure 26-15. To change the EEE protection that will be loaded during the reset
sequence, the P-Flash sector containing the EEE protection byte must be unprotected, then the EEE
protection byte must be programmed. If a double bit fault is detected while reading the P-Flash phrase
Table 26-22. P-Flash Protection Scenario Transitions
From
Protection
Scenario
To Protection Scenario1
1 Allowed transitions marked with X, see Figure 26-14 for a denition of the scenarios. 01234567
0
XXXX
1
XX
2
XX
3
X
4
XX
5
XXXX
6
XX
7
XXXXXXXX
Offset Module Base + 0x0009
76543210
R
EPOPEN
RNV[6:4]
EPDIS
EPS[2:0]
W
Reset
F
FFFFFF
= Unimplemented or Reserved
Figure 26-15. EEE Protection Register (EPROT)