MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3 Freescale Se" />
參數(shù)資料
型號(hào): MCF5207CVM166
廠商: Freescale Semiconductor
文件頁數(shù): 38/46頁
文件大?。?/td> 0K
描述: IC MCU 32BIT RISC 144-MAPBGA
標(biāo)準(zhǔn)包裝: 160
系列: MCF520x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166.67MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LBGA
包裝: 托盤
Revision History
MCF5208 ColdFire Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor
43
6
Revision History
Table 26. Revision History
Revision
Number
Date
Substantive Changes
0
5/23/2005
Initial Release
0.1
6/16/2005
Corrected 144QFP pinout in Figure 1. Pins 139-142 incorrectly showed
FEC functionality, which are actually UART 0/1 clear-to-send and
request-to-send signals.
Changed maximum core frequency in Table 10, spec #2, from 240MHz to
166.67MHz. Also, changed symbols in table: fcore -> fsys and fsys -> fsys/2
for consistency throughout document and reference manual.
0.2
8/26/2005
Changed ball M9 from SD_VDD to EVDD in Figure 9.
Table 3: Pin 33 for 144 LQFP package should be EVDD instead of
SD_VDD. BE/BWE[3:0] for 144 LQFP should be “20, 48, 18, 50“ instead
of “18, 20, 48, 50”
Cleaned up various electrical specifications:
Table 4: Added DDR/Memory pad supply voltage spec, changed “clock
synthesizer supply voltage” to “PLL supply voltage”, changed min PLLVDD
from -0.5 to -0.3, changed max VIN from 4.0 to 3.6, changed minimum Tstg
from -65 to -55,
Table 5: Changed TBD values in Tj entry to 105°C.
Table 7: Changed minimum core supply voltage from 1.35 to 1.4 and
maximum from 1.65 to 1.6, added PLL supply voltage entry, added pad
supply entries for mobile-DDR, DDR, and SDR, changed minimum input
high voltage from 0.7xEVDD to 2 and maximum from 3.65 to EVDD+0.05,
changed minimum input low voltage from VSS-0.3 to -0.05 and maximum
from 0.35xEVDDto 0.8, added input high/low voltage entries for DDR and
mobile-DDR, removed high impedance leakage current entry, changed
minimum output high voltage from EVDD-0.5 to EVDD-0.4, added DDR/bus
output high/low voltage entries, removed load capacitance and DC
injection current entries.
Added filtering circuits and voltage sequencing sections: Section 5.4.1,
Removed “Operating Conditions” table from Section 5.6, “Oscillator and
PLL Electrical Characteristics,because it is redundant with Table 7.
Table 11: Changed minimum core frequency to TBD, removed external
reference and on-chip PLL frequency specs to have only a CLKOUT
frequency spec of TBD to 83.33MHz, removed loss of reference frequency
and self-clocked mode frequency entries, in EXTAL input high/low voltage
entries changed “All other modes (Dual controller (1:1), Bypass, External)”
to “All other modes (External, Limp)”, removed XTAL output high/low
voltage entries, removed power-up to lock time entry, removed last 5
entries (frequency un-lock range, frequency lock range, CLKOUT period
jitter, frequency modulation range limit, and ICO frequency)
0.3
9/07/2005
Corrected DRAMSEL footnote #3 in Table 3.
Updated Table 3 with 144MAPBGA pin locations.
Added 144MAPBGA ballmap to Section 4.3, “Pinout—144 MAPBGA.
Changed J12 from PLL_VDD to IVDD in Figure 9.
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