參數(shù)資料
型號: MCF52110CAF80
廠商: Freescale Semiconductor
文件頁數(shù): 16/56頁
文件大?。?/td> 0K
描述: IC MCU 128K FLASH 80MHZ 100LQFP
標準包裝: 90
系列: MCF521xx
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 66MHz
連通性: I²C,SPI,UART/USART
外圍設備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: M5211DEMO-ND - KIT DEMO FOR MCF5211
Family Configurations
MCF52110 ColdFire Microcontroller, Rev. 1
Freescale Semiconductor
23
1.12
General Purpose Timer Signals
Table 14 describes the general purpose timer signals.
1.13
Pulse Width Modulator Signals
Table 15 describes the PWM signals.
1.14
Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 14. GPT Signals
Signal Name
Abbreviation
Function
I/O
General Purpose Timer
Input/Output
GPT[3:0]
Inputs to or outputs from the general purpose timer module.
I/O
Table 15. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channels
PWM[7:0]
Pulse width modulated output for PWM channels.
O
Table 16. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
JTAG Enable
JTAG_EN
Select between debug module and JTAG signals at reset.
I
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality),
asserting BKPT generates a debug interrupt exception in the
processor.
I
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