參數(shù)資料
型號(hào)： MCF52211CAE80
廠商： Freescale Semiconductor
文件頁數(shù)： 2/56頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 80MHZ 64-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： MCF5221x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 80MHz
連通性： I²C，SPI，UART/USART，USB OTG
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 43
程序存儲(chǔ)器容量： 128KB（128K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： M52210DEMO-ND - BOARD DEV MCF5221X LOW COST
M52211EVB-ND - BOARD EVAL FOR MCF52211
Family Configurations
MCF52211 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
10
1.2.7
USB On-The-Go Controller
The device includes a Universal Serial Bus On-The-Go (USB OTG) dual-mode controller. USB is a popular standard for
connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host PCs.
The OTG supplement to the USB specification extends USB to peer-to-peer application, enabling devices to connect directly
to each other without the need for a PC. The dual-mode controller on the device can act as a USB OTG host and as a USB
device. It also supports full-speed and low-speed modes.
1.2.8
UARTs
The device has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock,
eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O
functions.
1.2.9
I2C Bus
The processor includes two I2C modules. The I2C bus is an industry-standard, two-wire, bidirectional serial bus that provides
a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for
applications requiring occasional communications over a short distance between many devices.
1.2.10
QSPI
The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability.
It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.
1.2.11
Fast ADC
The fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold (S/H) circuits feeding
separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.
The ADC can be configured to perform a single scan and halt, a scan when triggered, or a programmed scan sequence repeatedly
until manually stopped.
The ADC can be configured for sequential or simultaneous conversion. When configured for sequential conversions, up to eight
channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a
scan, depending on the inputs to be sampled.
During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This
configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.
Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low
threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.
1.2.12
DMA Timers (DTIM0–DTIM3)
There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the device. Each
module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to
operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected,
it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler that clocks the actual
timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode.
Timer events may optionally cause interrupt requests or DMA transfers.
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