參數(shù)資料
型號(hào): MCF52211CAE80
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 28/56頁(yè)
文件大小: 0K
描述: IC MCU 32BIT 80MHZ 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: MCF5221x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 80MHz
連通性: I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 43
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤(pán)
配用: M52210DEMO-ND - BOARD DEV MCF5221X LOW COST
M52211EVB-ND - BOARD EVAL FOR MCF52211
Electrical Characteristics
MCF52211 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
34
2.9
USB Operation
2.10
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, Interrupt and USB interfaces. When in GPIO
mode, the timing specification for these pins is given in Table 30 and Figure 5.
The GPIO timing is met under the following load test conditions:
50 pF / 50
for high drive
25 pF / 25
for low drive
Frequency un-LOCK range
fUL
–1.5
1.5
% fref
Frequency LOCK range
fLCK
–0.75
0.75
% fref
CLKOUT period jitter 4, 5, 10 ,11, measured at fSYS Max
Peak-to-peak (clock edge to clock edge)
Long term (averaged over 2 ms interval)
Cjitter
10
.01
% fsys
On-chip oscillator frequency
foco
7.84
8.16
MHz
1 In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
2 This value has been updated.
3 All internal registers retain data at 0 Hz.
4 Depending on packaging; see the orderable part number summary.
5 Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
6 Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
LOR with
default MFD/RFD settings.
7 This parameter is characterized before qualification rather than 100% tested.
8 Proper PC board layout procedures must be followed to achieve specifications.
9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the Cjitter percentage
for a given interval.
11 Based on slow system clock of 40 MHz measured at f
sys max.
Table 29. USB Operation Specifications
Characteristic
Symbol
Value
Unit
Minimum core speed for USB operation
fsys_USB_min
16
MHz
Table 28. Oscillator and PLL Electrical Specifications (continued)
(VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V)
Characteristic
Symbol
Min
Max
Unit
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