參數(shù)資料
型號: MCF5235CVF150
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝: ROHS COMPLIANT, MAPBGA-256
文件頁數(shù): 2/48頁
文件大小: 666K
代理商: MCF5235CVF150
MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor
10
5.2
Power Supply
33
μF, 0.1 μF, and 0.01 μF across each power supply
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 1 shows situations in sequencing the I/O VDD (OVDD), PLL VDD (VDDPLL), and Core VDD (VDD).
OVDD is specified relative to VDD.
Figure 1. Supply Voltage Sequencing and Separation Cautions
5.2.1.1
Power Up Sequence
If OVDD is powered up with VDD at 0 V, then the sense circuits in the I/O pads cause all pad output drivers
connected to the OVDD to be in a high impedance state. There is no limit on how long after OVDD powers
up before VDD must power up. VDD should not lead the OVDD or VDDPLL by more than 0.4 V during
power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the
power supplies should be slower than 1
μs to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1 ms or slower rise time for all supplies.
2. VDD and OVDD/VDDPLL should track up to 0.9 V, then separate for the completion of ramps with
OVDD going to the higher external voltages. One way to accomplish this is to use a low drop-out
voltage regulator.
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
VDD should not exceed OVDD or VDDPLL by more than 0.4 V
at any time, including power-up.
Recommended that VDD should track OVDD/VDDPLL up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
1.
2.
3.
4.
DC
P
o
w
e
rSuppl
y
V
o
lt
a
g
e
VDD
OVDD, VDDPLL
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