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參數(shù)資料
| 型號： | MCF5235CVF150 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | ROHS COMPLIANT, MAPBGA-256 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 666K |
| 代理商： | MCF5235CVF150 |
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
28
7.5
External Interface Timing Characteristics
Table 11 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
7
This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
8
Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
9
tlpll = (64 * 4 * 5 + 5 × τ) × Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and
τ = 1.57x10-6
× 2(MFD + 2).
10 PLL is operating in 1:1 PLL mode.
11 Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a
stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in
crystal oscillator frequency increase the Cjitter percentage for a given interval.
12 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.
13 Modulation percentage applies over an interval of 10
μs, or equivalently the modulation rate is 100KHz.
14 Modulation rate selected must not result in f
sys/2 value greater than the fsys/2 maximum specified value.
Modulation range determined by hardware design.
15 f
sys/2 = fico / (2 * 2
RFD)
Table 11. Processor Bus Input Timing Specifications
Name
Characteristic1
1
Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
environment..
Symbol
Min
Max
Unit
freq
System bus frequency
fsys/2
50
75
MHz
B0
CLKOUT period
tcyc
—1/75
ns
Control Inputs
B1a
Control input valid to CLKOUT high2
2
TEA and TA pins are being referred to as control inputs.
tCVCH
9—
ns
B1b
BKPT valid to CLKOUT high3
3
Refer to figure A-19.
tBKVCH
9—
ns
B2a
CLKOUT high to control inputs invalid2
tCHCII
0—
ns
B2b
CLKOUT high to asynchronous control input BKPT invalid3
tBKNCH
0—
ns
Data Inputs
B4
Data input (D[31:0]) valid to CLKOUT high
tDIVCH
4—
ns
B5
CLKOUT high to data input (D[31:0]) invalid
tCHDII
0—
ns
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| MCF5235CVM100 | 功能描述:微處理器 - MPU MCF5235 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| MCF5235CVM150 | 功能描述:IC MPU 32BIT COLDF 256-MAPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MCF523x 標(biāo)準(zhǔn)包裝:330 系列:- 核心處理器:- 芯體尺寸:8/16-位 速度:40MHz 連通性:UART/USART 外圍設(shè)備:DMA，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:- 程序存儲器類型:外部程序存儲器 EEPROM 大小:- RAM 容量:- 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-BQFP 包裝:管件 |
| MCF5235CVM150 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
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