參數(shù)資料
型號: MCF5274LVM166J
廠商: Freescale Semiconductor
文件頁數(shù): 24/44頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 166MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝: 126
系列: MCF527x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166MHz
連通性: EBI/EMI,以太網(wǎng),I²C,SPI,UART/USART,USB
外圍設(shè)備: DMA,WDT
輸入/輸出數(shù): 61
程序存儲器類型: ROMless
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 196-LBGA
包裝: 托盤
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Electrical Characteristics
Freescale Semiconductor
30
Figure 13 shows a DDR SDRAM write cycle.
Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing
DD13
DQS input read preamble width (tRPRE)tRPRE
0.9
1.1
tCK
DD14
DQS input read postamble width (tRPST)tRPST
0.4
0.6
tCK
DD15
DQS output write preamble width (tWPRE)tWPRE
0.25
tCK
DD16
DQS output write postamble width (tWPST)tWPST
0.4
0.6
tCK
1
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2
DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
3
tCKH + tCKL must be less than or equal to tCK.
4
D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
5
The first data beat is valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The remaining
data beats are valid for each subsequent SD_DQS edge
6
Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
7
Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
line becomes invalid.
Table 15. DDR Timing (continued)
NUM
Characteristic1
Symbol
Min
Max
Unit
DDR_CLKOUT
VIX
VMP
VIX
VID
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