參數(shù)資料
型號(hào)： MCF53014CMJ240J
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 39/62頁(yè)
文件大小： 0K
描述： IC MCU 32BIT 128KB 256MAPBGA
標(biāo)準(zhǔn)包裝： 450
系列： MCF5301x
核心處理器： Coldfire V3
芯體尺寸： 32-位
速度： 240MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB，USB OTG
外圍設(shè)備： DMA，PWM，WDT
輸入/輸出數(shù)： 83
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類(lèi)型： 緩存
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.08 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
包裝： 托盤(pán)
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
44
5.17.2
Reset Sequence
5.17.2.1
Cards with Internal Reset
The reset sequence for this kind of SIM card is as follows (see Figure 31):
After powerup, the clock signal is enabled on SIM_CLK (time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40,000 clock cycles after T0.
Figure 31. Internal-Reset Card Reset Sequence
5.17.2.2
Cards with Active-Low Reset
The sequence of reset for this kind of card is as follows (see Figure 32):
1.
After powerup, the clock signal is enabled on SIM_CLK (time T0)
2.
After 200 clock cycles, RX must be high.
3.
SIM_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those
40,000 clock cycles)
4.
SIM_RST is set high (time T1)
5.
SIM_RST must remain high for at least 40,000 clock cycles after T1 and a response must be received on RX between
400 and 40,000 clock cycles after T1.
Table 29. SIM Timing Specification—High Drive Strength
Num
Description
Symbol
Min
Max
Unit
1
SIM Clock Frequency (SIM_CLK)1
1 50% duty cycle clock
Sfreq
0.01
5 (Some new cards
may reach 10)
MHz
2
SIM_CLK Rise Time 2
2 With C = 50pF
Srise
–20
ns
3
SIM_CLK Fall Time 3
3 With C = 50pF
Sfall
–20
ns
4
SIM Input Transition Time (RX, SIM_PD)
Strans
–25
ns
SIM_VEN
SIM_CLK
SIM_RX
2
T0
1
Response
2
1
< 200 clock cycles
< 40,000 clock cycles
400 clock cycles <
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