參數(shù)資料
型號: MCF54418CMJ250
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA256
封裝: 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁數(shù): 30/60頁
文件大?。?/td> 1107K
代理商: MCF54418CMJ250
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
36
All ULPI signals use pad type pad_fsr. The following timing specifications assume a pad slew rate setting of 11 and a load of
50 pF.1
Figure 19. ULPI timing diagram
4.15
eSDHC timing specifications
This section describes the electrical information of the eSDHC.
All eSDHC signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load
of 50 pF.2
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 19. ULPI interface timing
Num
Characteristic
Min
Nominal
Max
Units
USB_CLKIN operating frequency
60
MHz
USB_CLKIN duty cycle
50
%
U1
USB_CLKIN clock period
16.67
ns
U2
Input setup (control and data)
5.0
ns
U3
Input hold (control and data)
1.0
ns
U4
Output valid (control and data)
9.5
ns
U5
Output hold (control and data)
1.0
ns
2.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
ULPI_DATA[7:0]
(Data Output)
ULPI_DATA[7:0]
(Data Input)
ULPI_DIR / ULPI_NXT
(Control Input)
ULPI_STP
(Control Output)
USB_CLKIN
U1
U2
U3
U4
U5
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