參數(shù)資料
型號(hào)： MCF54418CMJ250
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, PBGA256
封裝： 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁數(shù)： 48/60頁
文件大?。?/td> 1107K
代理商： MCF54418CMJ250
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
52
4.25
SBF timing specifications
The Serial boot facility (SBF) provides a means to read configuration information and system boot code from a broad array of
SPI-compatible EEPROMs, flashes, FRAMs, nVSRAMs, etc. Table 37 provides the AC timing specifications for the SBF.
All SBF signals use pad type pad_msr. The following timing specifications assume a pad slew rate setting of 11 and a load of
50 pF.1
Figure 34. SBF timing
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 37. SBF AC timing specifications
Name
Characteristic
Symbol
Min
Max
Unit
Notes
—
SBF_CK frequency
fSBFCK
—
62.5
MHz
SB1
SBF_CK cycle time
tSBFCK
16.67
—
ns
1
1 At reset, the SBF_CK cycle time is t
REF 60. The first byte of data read from the serial memory contains a divider value
that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB2
SBF_CK high/low time
—
30%
—
tSBFCK
SB3
SBF_CS to SBF_CK delay
—
tSBFCK – 2.0
—
ns
SB4
SBF_CK to SBF_CS delay
—
tSBFCK – 2.0
—
ns
SB5
SBF_CK to SBF_DO valid
—
5
ns
SB6
SBF_CK to SBF_DO invalid
—
–5
—
ns
SB7
SBF_DI to SBF_SCK input setup
—
10
—
ns
SB8
SBF_CK to SBF_DI input hold
—
0
—
ns
SBF_CS
SBF_DO
SBF_DI
Data
Last Data
First Data
Data
Last Data
SB3
SB4
SB6
SB5
SBF_CK
SB1
SB2
SB7
SB8
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參數(shù)描述
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