參數(shù)資料
型號: MCHC11F1CFNE5
廠商: Freescale Semiconductor
文件頁數(shù): 91/158頁
文件大?。?/td> 0K
描述: MCU 8BIT 1KRAM 512EE 68-PLCC
標(biāo)準(zhǔn)包裝: 18
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 5MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器類型: ROMless
EEPROM 大?。?/td> 512 x 8
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
CENTRAL PROCESSING UNIT
MC68HC11F1
3-14
TECHNICAL DATA
STAB (opr)
Store
Accumulator
B
M
B
DIR
B
EXT
B
IND,X
B
IND,Y
D7
F7
E7
18
E7
dd
hh ll
ff
3
4
5
————
0—
STD (opr)
Store
Accumulator
D
A
M, B M + 1
DIR
EXT
IND,X
IND,Y
DD
FD
ED
18
ED
dd
hh ll
ff
4
5
6
————
0—
STOP
Stop Internal
Clocks
INH
CF
2
————————
STS (opr)
Store Stack
Pointer
SP
M : M + 1
DIR
EXT
IND,X
IND,Y
9F
BF
AF
18
AF
dd
hh ll
ff
4
5
6
————
0—
STX (opr)
Store Index
Register X
IX
M : M + 1
DIR
EXT
IND,X
IND,Y
DF
FF
EF
CD
EF
dd
hh ll
ff
4
5
6
————
0—
STY (opr)
Store Index
Register Y
IY
M : M + 1
DIR
EXT
IND,X
IND,Y
18
DF
18
FF
1A
EF
18
EF
dd
hh ll
ff
5
6
————
0—
SUBA (opr)
Subtract
Memory from
A
A – M
A
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
80
90
B0
A0
18
A0
ii
dd
hh ll
ff
2
3
4
5
————
SUBB (opr)
Subtract
Memory from
B
B – M
B
A
IMM
A
DIR
A
EXT
A
IND,X
A
IND,Y
C0
D0
F0
E0
18
E0
ii
dd
hh ll
ff
2
3
4
5
————
SUBD (opr)
Subtract
Memory from
D
D – M : M + 1
D
IMM
DIR
EXT
IND,X
IND,Y
83
93
B3
A3
18
A3
jj kk
dd
hh ll
ff
4
5
6
7
————
SWI
Software
Interrupt
See Figure 3–2
INH
3F
14
1
————
TAB
Transfer A to B
A
B
INH
16
2
————
0—
TAP
Transfer A to
CC Register
A
CCR
INH
06
2
TBA
Transfer B to A
B
A
INH
17
2
————
0—
TEST
TEST (Only in
Test Modes)
Address Bus Counts
INH
00
*
————————
TPA
Transfer CC
Register to A
CCR
A
INH
07
2
————————
TST (opr)
Test for Zero
or Minus
M – 0
EXT
IND,X
IND,Y
7D
6D
18
6D
hh ll
ff
6
7
————
00
TSTA
Test A for Zero
or Minus
A – 0
A
INH
4D
2
————
00
TSTB
Test B for Zero
or Minus
B – 0
B
INH
5D
2
————
00
TSX
Transfer
Stack Pointer
to X
SP + 1
IX
INH
30
3
————————
TSY
Transfer
Stack Pointer
to Y
SP + 1
IY
INH
18
30
4
————————
TXS
Transfer X to
Stack Pointer
IX – 1
SP
INH
35
3
————————
TYS
Transfer Y to
Stack Pointer
IY – 1
SP
INH
18
35
4
————————
WAI
Wait for
Interrupt
Stack Regs & WAIT
INH
3E
**
————————
XGDX
Exchange D
with X
IX
D, D IX
INH
8F
3
————————
XGDY
Exchange D
with Y
IY
D, D IY
INH
18
8F
4
————————
Table 3-2 Instruction Set (Sheet 6 of 6)
Mnemonic
Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode
Operand
Cycles
S
X
H
I
N
Z
V
C
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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