參數(shù)資料
型號： MCHC705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 114/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Low-Power Modes
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
53
6.3.2 Wait Mode
The WAIT instruction puts the MCU in a low-power wait mode which consumes more power than the stop
mode and affects the MCU as follows:
Enables interrupts by clearing the I bit in the condition code register
Enables external interrupts by setting the IRQE bit in the IRQ status and control register
Stops the CPU clock which drives the address and data buses, but allows the selected oscillator
to continue to clock the core timer, programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O lines.
These conditions restart the CPU bus clock and bring the MCU out of wait mode:
An external interrupt signal on the IRQ/VPP pin — A high-to-low transition on the IRQ/VPP pin loads
the program counter with the contents of locations $1FFA and $1FFB.
An external interrupt signal on a port A external interrupt pin — If selected by PIRQ bit in the MOR,
a low-to-high transition on a PA3–PA0 pin loads the program counter with the contents of locations
$1FFA and $1FFB.
A core timer interrupt — A core timer overflow or a real-time interrupt loads the program counter
with the contents of locations $1FF8 and $1FF9.
A programmable timer interrupt — A programmable timer interrupt driven by an input capture,
output compare, or timer overflow loads the program counter with the contents of locations $1FF6
and $1FF7.
An SIOP interrupt — An SIOP interrupt driven by the completion of transmitted or received 8-bit
data loads the program counter with the contents of locations $1FF4 and $1FF5.
An analog subsystem interrupt — An analog subsystem interrupt driven by a voltage comparison
loads the program counter with the contents of locations $1FF2 and $1FF3.
A COP watchdog reset — A timeout of the COP watchdog resets the MCU and loads the program
counter with the contents of locations $1FFE and $1FFF. Software can enable real-time interrupts
so that the MCU can periodically exit the wait mode to reset the COP watchdog.
An external reset — A logic 0 on the RESET pin resets the MCU and loads the program counter
with the contents of locations $1FFE and $1FFF.
When the MCU exits the wait mode, there is no delay before code executes like occurs when exiting the
stop or halt modes.
6.3.3 Halt Mode
The STOP instruction puts the MCU in halt mode if selected by the SWAIT bit in the MOR. Halt mode is
identical to wait mode, except that a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the DELAY bit in
the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP watchdog cannot be turned off
inadvertently by a STOP instruction.
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