參數(shù)資料
型號： MCHC705JP7CDWE
廠商： Freescale Semiconductor
文件頁數(shù)： 95/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28SOIC
標(biāo)準(zhǔn)包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Interrupts
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
36
Freescale Semiconductor
4.4 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.5 External Interrupts
These sources can generate external interrupts:
IRQ/VPP pin
PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control
register disables these external interrupts.
4.5.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt request. To help clean up slow edges,
the input from the IRQ/VPP pin is processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the
IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches
the interrupt vector, so that another external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 4-3 shows the logic for external interrupts.
NOTE
If the IRQ/VPP pin is not in use, it should be connected to the VDD pin.
The IRQ/VPP pin can be negative edge-triggered only or negative edge- and low level-triggered. External
interrupt sensitivity is programmed with the LEVEL bit in the mask option register (MOR).
With the edge- and level-sensitive trigger MOR option, a falling edge or a low level on the IRQ/VPP pin
latches an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection
to the IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ low,
an external interrupt request is present, and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the IRQ/VPP pin latches an external interrupt
request. A subsequent interrupt request can be latched only after the voltage level on the IRQ/VPP pin
returns to a logic 1 and then falls again to logic 0.
NOTE
The response of the IRQ/VPP pin can be affected if the external interrupt
capability of the PA0 through PA3 pins is enabled. If the port A pins are
enabled as external interrupts, then any high level on a PA0–PA3 pin will
cause the IRQ changes and state to be ignored until all of the PA0–PA3
pins have returned to a low level.
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