參數(shù)資料
型號: MCIMX257CJN4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA347
封裝: 12 X 12 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-347
文件頁數(shù): 136/154頁
文件大?。?/td> 1498K
代理商: MCIMX257CJN4A
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
82
Freescale Semiconductor
Figure 53 shows the ESAI HCKR timing diagram.
Figure 53. ESAI HCKR Timing
Table 60 describes the general timing requirements for the ESAI module. Table 58 and Table 59 describe
respectively the conditions and signals cited in Table 60.
Table 58. ESAI Timing Conditions
Symbol
Significance
Comments
i ck
Internal clock
In the i.MX25, the internal clock frequency is equal to the IP bus frequency
(133 MHz)
x ck
External clock
The external clock may be derived from the CRM module or other external
clock sources
i ck a
Internal clock, asynchronous mode
In asynchronous mode, SCKT and SCKR are different clocks
i ck s
Internal clock, synchronous mode
In synchronous mode, SCKT and SCKR are the same clock
Table 59. ESAI Signals
Signal Name
Significance
SCKT
Transmit clock
SCKR
Receive clock
FST
Transmit frame sync
HCKT
Transmit high-frequency clock
HCKR
Receive high-frequency clock
Table 60. ESAI General Timing Requirements
No.
Characteristics1 2
Symbol
Expression3
Min.
Max.
Condition
Unit
62
Clock cycle4
tSSICC
4
× T
c
4
× T
c
30.0
i ck
ns
63
Clock high period
For internal clock
2
× T
c 9.0
6
—ns
For external clock
2
× Tc
15
64
Clock low period
For internal clock
—2
× T
c 9.0
6
—ns
For external clock
2
× T
c
15
HCKR
SCKR (output)
97
95
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