參數(shù)資料
型號(hào): MCIMX257CJN4A
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA347
封裝: 12 X 12 MM, 0.50 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-347
文件頁數(shù): 17/154頁
文件大小: 1498K
代理商: MCIMX257CJN4A
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Freescale Semiconductor
113
assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive
conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.
Figure 82. Start-up Sequence
The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising
edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,
xnsw) are totally asynchronous.
The following conditions are necessary to guarantee the correct operation of the ADC:
The input multiplexer selection (selin11…selin0) is stable during both the last clock cycle (14th)
and the first clock cycle (1st). The best way to guarantee this is to make the input multiplexer
selection during clock cycles 2 to 13.
The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the
reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it
only after an eoc pulse has been acquired, during the last clock cycle (14).
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