參數(shù)資料
型號： MCIMX27MJP4A
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA473
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MAPBGA-473
文件頁數(shù)： 96/152頁
文件大?。?/td> 3889K
代理商： MCIMX27MJP4A
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
48
Freescale Semiconductor
Electrical Characteristics
4.2.3
ATA Electrical Specifications
This section describes the electrical information of the Parallel ATA module compliant with ATA/ATAPI-6
specification.
NOTE
The parallel ATA module is not available on the i.MX27L
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100 MB/s. Parallel ATA
module interface consist of a total of 29 pins, Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Below defines the AC characteristics of all the interface signals on all data transfer modes.
4.2.3.1
General Timing Requirements
These are the general timing requirements for the ATA interface signals.
Table 19. Write 1/Read Timing Parameters
ID
Parameter
Symbol
Min
Typical
Max
Units
OW7
Write 1/Read Low Time
tLOW1
15
s
OW8
Transmission Time Slot
tSLOT
60
117
120
s
OW9
Release Time
tRELEASE
15
—
45
s
Table 20. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min
Max
Unit
SI1
Rising edge slew rate for any signal on ATA
interface (see note)
Srise
—
1.25
V/ns
SI2
Falling edge slew rate for any signal on ATA
interface (see note)
Sfall
—
1.25
V/ns
SI3
Host interface signal capacitance at the host
connector
Chost
—20
pF
Note: SRISE and SFALL meets this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.
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