參數(shù)資料
型號(hào)： MCIMX27MOP4A
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 142/152頁(yè)
文件大?。?/td> 0K
描述： IC MPU I.MX27 19X19 473MAPBGA
標(biāo)準(zhǔn)包裝： 84
系列： i.MX27
核心處理器： ARM9
芯體尺寸： 32-位
速度： 400MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，LCD，POR，PWM，WDT
程序存儲(chǔ)器類型： ROMless
RAM 容量： 45K x 8
電壓 - 電源 (Vcc/Vdd)： 1.38 V ~ 1.52 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 473-LFBGA
包裝： 托盤
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i.MX27 and i.MX27L Data Sheet, Rev. 1.8
Freescale Semiconductor
9
Functional Description and Application Information
2.3
Module Descriptions
This section provides a brief text description of all the modules included in the i.MX27/MX27L devices,
arranged in alphabetical order.
2.3.1
1-Wire Module
The 1-Wire module provides bi-directional communication between the ARM926 core and the Add-Only
Memory EPROM, DS2502. The 1-Kbit EPROM holds information about the battery and communicates
with the ARM926 Platform using the IP interface. Through the 1-Wire interface, the ARM926 acts as the
bus master while the DS2502 device is the slave. The 1-Wire peripheral does not trigger interrupts; hence
it is necessary for the ARM926 to poll the 1-Wire to manage the module. The 1-Wire uses an external pin
to connect to the DS2502. Timing requirements are met in hardware with the help of a 1 MHz clock. The
clock divider generates a 1 MHz clock that is used as a time reference by the state machine. Timing
requirements are crucial for proper operation, and the 1-Wire state machine and the internal clock provide
the necessary signal. The clock must be configured to approximately 1 MHz. You can then set the 1-Wire
register to send and receive bits over the 1-Wire bus.
USB
Universal Serial
Bus–2 Host
Controllers and
1 OTG
(On-The-Go)
Connectivity
Peripherals
The i.MX27/MX27L processors provide two USB Host
controllers and one USBOTG of which:
USB Host 1 is designed to support transceiverless
connection to the on-board peripherals in Low Speed and
Full Speed mode, and connection to the ULPI
(UTMI+Low-Pin Court) and Legacy Full Speed transceivers
USB Host 2 is designed to support transceiverless
connection to the Cellular Modem Baseband Processor
The USBOTG controller offers HS/FS/LS capabilities in Host
mode and HS/FS in device mode. In Host mode, the
controller supports direct connection of a FS/LS device
(without external hub). In device (bypass) mode, the OTG
port functions as gateway between the Host 1 Port and the
OTG transceiver.
Video Codec
Hardware
Acceleration
Video Codec module supports full duplex video codec with 25
fps VGA image resolution, integrates H.264 BP, MPEG-4 SP
and H.263 P3 video processing standard together.
WDOG
Watchdog Timer
Module
Timer
Peripheral
The WDOG module protects against system failures by
providing a method for the system to recover from unexpected
events or programming errors.
WEIM
Wireless
External
Interface
Module
External
Memory
Interface
The Wireless External Module (WEIM) handles the interface to
devices external to chip, including generation of chip selects,
clock and control for external peripherals and memory. It
provides asynchronous and synchronous access to devices
with SRAM-like interface.
Table 2. Digital and Analog Modules (continued)
Block Mnemonic
Block Name
Functional
Grouping
Brief Description
Section/
Page
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