參數(shù)資料
型號: MCIMX31DVMN5D
廠商: Freescale Semiconductor
文件頁數(shù): 91/118頁
文件大?。?/td> 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標準包裝: 84
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 托盤
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
74
Freescale Semiconductor
Electrical Characteristics
Figure 59. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Table 49. Asynchronous Parallel Interface Timing Parameters—Access Level
ID
Parameter
Symbol
Min.
Typ.1
Max.
Units
IP27 Read system cycle time
Tcycr
Tdicpr–1.5
Tdicpr2
Tdicpr+1.5
ns
IP28 Write system cycle time
Tcycw
Tdicpw–1.5
Tdicpw3
Tdicpw+1.5
ns
IP29 Read low pulse width
Trl
Tdicdr–Tdicur–1.5
Tdicdr4–Tdicur5
Tdicdr–Tdicur+1.5
ns
IP30 Read high pulse width
Trh
Tdicpr–Tdicdr+Tdicur–1.5 Tdicpr–Tdicdr+
Tdicur
Tdicpr–Tdicdr+Tdicur+1.5
ns
IP31 Write low pulse width
Twl
Tdicdw–Tdicuw–1.5
Tdicdw6–Tdicuw7
Tdicdw–Tdicuw+1.5
ns
IP32 Write high pulse width
Twh
Tdicpw–Tdicdw+
Tdicuw–1.5
Tdicpw–Tdicdw+
Tdicuw
Tdicpw–Tdicdw+
Tdicuw+1.5
ns
IP33 Controls setup time for read
Tdcsr
Tdicur–1.5
Tdicur
ns
IP34 Controls hold time for read
Tdchr
Tdicpr–Tdicdr–1.5
Tdicpr–Tdicdr
ns
IP35 Controls setup time for write
Tdcsw
Tdicuw–1.5
Tdicuw
ns
IP28, IP27
Read Data
IP32, IP30
IP37
IP38
DISPB_PAR_RS
DISPB_DATA
DISPB_WR
(Input)
(Output)
IP35,IP33
IP36, IP34
IP31, IP29
IP40
IP39
IP45, IP43
IP42, IP41
DISPB_RD (ENABLE_L)
DISPB_D#_CS
(READ/WRITE)
DISPB_DATA[17]
(ENABLE_H)
read point
IP46,IP44
IP47
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