參數(shù)資料
型號: MCIMX31DVMN5DR2
廠商: Freescale Semiconductor
文件頁數(shù): 52/118頁
文件大?。?/td> 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標準包裝: 750
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Freescale Semiconductor
39
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Timing for HCLK is 133 MHz and internal NFC clock (flash clock) is
approximately 33 MHz (30 ns). All timings are listed according to this NFC
clock frequency (multiples of NFC clock phases), except NF16 and NF17,
which are not NFC clock related.
4.3.9.2
Wireless External Interface Module (WEIM)
All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising
edge or falling edge according to corresponding assertion/negation control fields. Address always begins
related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according
to control register configuration. Output data begins related to BCLK rising edge except in muxed mode
where both rising and falling edge may be used according to control register configuration. Input data,
ECB and DTACK all captured according to BCLK rising edge time. Figure 26 depicts the timing of the
WEIM module, and Table 32 lists the timing parameters.
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MCIMX31LCVKN5C 功能描述:IC MPU MAP I.MX31L 457-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:i.MX31 標準包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C,SPI,UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位,POR,PWM,WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB(16K x 16) 程序存儲器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT