參數(shù)資料
型號: MCIMX31DVMN5DR2
廠商: Freescale Semiconductor
文件頁數(shù): 67/118頁
文件大?。?/td> 0K
描述: IC MPU I.MX31 CONSUMR 473MAPBGA
標準包裝: 750
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
52
Freescale Semiconductor
Electrical Characteristics
Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
NOTE
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 38 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
4.3.10
ETM Electrical Specifications
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that
supports TRACECLK frequencies up to 133 MHz.
Figure 39 depicts the TRACECLK timings of ETM, and Table 39 lists the timing parameters.
Figure 39. ETM TRACECLK Timing Diagram
Table 38. Mobile DDR SDRAM Read Cycle Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
tDQSQ
0.85
ns
SD22 DQS DQ HOLD time from DQS
tQH
2.3
ns
SD23 DQS output access time from SDCLK posedge
tDQSCK
6.7
ns
SDCLK
DQS (input)
DQ (input)
Data
SD23
SD21
SD22
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