參數(shù)資料
型號: MCIMX31VMN5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 107/122頁
文件大小: 0K
描述: IC MPU MAP I.MX31L 473-MAPBGA
標(biāo)準(zhǔn)包裝: 750
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
Electrical Characteristics
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
Freescale Semiconductor
85
Figure 68. Transfer Operation Timing Diagram (Parallel)
NOTE
The Memory Stick Host Controller is designed to meet the timing
requirements per Sony's Memory Stick Pro Format Specifications document.
Tables in this section details the specifications requirements for parallel and
serial modes, and not the MCIMX31 timing.
Table 52. Serial Interface Timing Parameters1
1 Timing is guaranteed for NVCC from 2.7 through 3.1 V and up to a maximum overdrive NVCC of 3.3 V. See
NVCC restrictions described in Table 8, "Operating Ranges," on page 13.
Signal
Parameter
Symbol
Standards
Unit
Min.
Max.
MSHC_SCLK
Cycle
tSCLKc
50
ns
H pulse length
tSCLKwh
15
ns
L pulse length
tSCLKwl
15
ns
Rise time
tSCLKr
10
ns
Fall time
tSCLKf
10
ns
MSHC_BS
Setup time
tBSsu
5
ns
Hold time
tBSh
5
ns
MSHC_DATA
Setup time
tDsu
5
ns
Hold time
tDh
5
ns
Output delay time
tDd
15
ns
tSCLKc
MSHC_SCLK
tBSsu
tBSh
tDsu
tDh
MSHC_BS
MSHC_DATA
(Output)
tDd
MSHC_DATA
(Intput)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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