參數(shù)資料
型號: MCIMX31VMN5CR2
廠商: Freescale Semiconductor
文件頁數(shù): 69/122頁
文件大?。?/td> 0K
描述: IC MPU MAP I.MX31L 473-MAPBGA
標(biāo)準(zhǔn)包裝: 750
系列: i.MX31
核心處理器: ARM11
芯體尺寸: 32-位
速度: 532MHz
連通性: 1 線,ATA,EBI/EMI,F(xiàn)IR,I²C,MMC/SD,PCMCIA,SIM,SPI,SSI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,LCD,POR,PWM,WDT
程序存儲器類型: ROMless
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.22 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 473-LFBGA
包裝: 帶卷 (TR)
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
50
Freescale Semiconductor
Electrical Characteristics
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 35 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Figure 36. SDRAM Refresh Timing Diagram
SD13
Data setup time
tDS
2.0
ns
SD14
Data hold time
tDH
1.3
ns
1 SD11 and SD12 are determined by SDRAM controller register settings.
Table 36. SDRAM Refresh Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
SD1
SDRAM clock high-level width
tCH
3.4
4.1
ns
SD2
SDRAM clock low-level width
tCL
3.4
4.1
ns
Table 35. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS
CAS
WE
RAS
ADDR
BA
ROW/BA
SD6
SD7
SD11
SD10
SDCLK
SD1
SD2
SDCLK
SD3
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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