參數(shù)資料
型號(hào)： MCIMX355AVM5BR2
廠商： Freescale Semiconductor
文件頁數(shù)： 113/147頁
文件大?。?/td> 0K
描述： IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX35
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲(chǔ)器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.33 V ~ 1.47 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 400-LFBGA
包裝： 帶卷 (TR)
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
68
inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.9.12.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.9.12.2.2, “Gated Clock Mode”),
except for the SENSB_HSYNC signal, which is not used. See Figure 45. All incoming pixel clocks are
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Figure 45. Non-Gated Clock Mode Timing Diagram
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
SENSB_DATA[9:0]
invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Active Line
Start of Frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[7:0]
invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Start of Frame
相關(guān)PDF資料
PDF描述
VI-BNH-IY-F3 CONVERTER MOD DC/DC 52V 50W
VE-B5D-IW-B1 CONVERTER MOD DC/DC 85V 100W
VI-BNF-IY-F4 CONVERTER MOD DC/DC 72V 50W
VI-BND-IY-F1 CONVERTER MOD DC/DC 85V 50W
S912XDP512F0MAL IC MCU 16BIT 512KB FLASH 112LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX356AJM5B 功能描述:開發(fā)板和工具包 - ARM RINGO MX35 TO2 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評(píng)估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V
MCIMX356AJM5BR2 功能描述:處理器 - 專門應(yīng)用 RINGO MX35 TO2 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX356AJQ4C 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX35 Applications Processors for Automotive Products
MCIMX356AJQ5C 功能描述:處理器 - 專門應(yīng)用 RINGO MX35 TO2.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX356AJQ5C 制造商:Freescale Semiconductor 功能描述:; LEADED PROCESS COMPATIBLE:YES; PEAK RE
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*